View S3056_1948551.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j bicmos pecl clock generator device specification multi-rate sonet/sdh clock recovery unit S3056 ? features ? sige bicmos technology ? complies with bellcore and itu-t specifica- tions for jitter tolerance, jitter transfer and jitter generation ? on-chip high frequency pll with internal loop filter for clock recovery ? supports clock recovery for: oc-48 (2488.32 mbps), fibre channel (2125 mbps), oc-24 (1244.16 mbps), gigabit ethernet (1250 mbps), fibre channel (1062.5 mbps), oc-12 (622.08 mbps), oc-3 (155.52 mbps) nrz data ? selectable reference frequencies 19.44 mhz or 155.52 mhz (or equivalent fibre channel/ gigabit ethernet frequencies) ? lock detectmonitors frequency of incoming data ? low-jitter serial interface ? +3.3 v supply ? compact 48 pin tqfp tep package ? typical power 620 mw general description the function of the S3056 clock recovery unit is to derive high speed timing signals for sonet/sdh- based equipment. the S3056 is implemented using amccs proven phase locked loop (pll) technology. figure 1 shows a typical network application. the S3056 receives an oc-48, oc-24, oc-12, oc-3, fibre channel or gigabit ethernet scrambled nrz sig- nal and recovers the clock from the data. the chip outputs a differential bit clock and retimed data. the S3056 utilizes an on-chip pll which consists of a phase detector, a loop filter, and a voltage controlled oscillator (vco). the phase detector compares the phase relationship between the vco output and the serial data input. a loop filter con- verts the phase detector output into a smooth dc voltage, and the dc voltage is input to the vco whose frequency is varied by this voltage. a block diagram is shown in figure 2. figure 1. system block diagram network interface processor network interface processor s3057 s3057 otx orx otx orx 16 16 16 16 S3056 S3056
2 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j S3056 overview the S3056 supports clock recovery for the oc-48, fibre channel (2125 mbps), oc-24, gigabit ethernet, fibre channel (1062.5 mbps), oc-12 or oc-3 data rate. differential serial data is input to the chip at the specified rate, and clock recovery is per- formed on the incoming data stream. an external os- cillator is required to minimize the pll lock time, and provide a stable output clock source in the absence of serial input data. retimed data and clock are output from the S3056. figure 2. S3056 functional block diagram 2 serclkop/n lockdet serdatop/n refclkp/n testclk lckrefn serdatip/n loop filter vco clock divider phase detector lock detector sdn cap 1,2 ratesel[1:0] refsel testen rst bypass 2 testout refcmp suggested interface devices sumitomo oc-48 optical receiver amcc s3057 oc-48 transceiver
3 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j S3056 functional description the S3056 clock recovery device performs the clock recovery function for sonet oc-48, fibre channel (2125 mbps), oc-24, gigabit ethernet, fibre channel (1062.5 mbps), oc-12 or oc-3 serial data links. the chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. a 155.52/19.44 mhz (156.25/19.53 mhz for gigabit ethernet and 132.81/16.60 mhz for fibre channel) reference clock is required for phase locked loop start up and proper operation under loss of signal conditions. an integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. the input data rate is selected by the ratesel inputs. (see table 1.) clock recovery clock recovery, as shown in the block diagram in figure 2, generates a clock that is at the same fre- quency as the incoming data bit rate at the serial data input. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transi- tions of the data and those of the generated clock are compared by a phase/frequency discriminator. output pulses from the discriminator indicate the required direction of phase corrections. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which generates the recovered clock. 0 l e s e t a r1 l e s e t a re d o m g n i t a r e p o k l c f e r y c n e u q e r f 0 0 1 1 1 1 1 0 1 0 1 0 0 1 3 - c o 2 1 - c o 4 2 - c o 8 4 - c o t e n r e h t e t i b a g i g l e n n a h c e r b i f l e n n a h c e r b i f 4 4 . 9 1 / 2 5 . 5 5 1 4 4 . 9 1 / 2 5 . 5 5 1 4 4 . 9 1 / 2 5 . 5 5 1 4 4 . 9 1 / 2 5 . 5 5 1 3 5 . 9 1 / 5 2 . 6 5 1 0 6 . 6 1 / 1 8 . 2 3 1 0 6 . 6 1 / 1 8 . 2 3 1 table 1. data rate select table 2. reference frequency select l e s f e ry c n e u q e r f e c n e r e f e r 0z h m 4 4 . 9 1 1z h m 2 5 . 5 5 1 frequency stability without incoming data is guaran- teed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by a value greater than that stated in table 7 with respect to refclkp/n, the pll will be declared out of lock, and the pll will lock to the reference clock. the assertion of sdn will also cause an out of lock condition. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance proposed for sonet equipment by the bellcore ta-nwt-000253 standard, shown in figure 3. lock detect the S3056 contains a lock detect circuit which monitors the integrity of the serial data inputs. if the received serial data fails the frequency test, the pll will be forced to lock to the local reference clock. this will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. if the recovered clock frequency deviates from the local reference clock frequency by more than that stated in table 7, the pll will be declared out of lock. the lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. if the recovered clock fre- quency is determined to be within that stated in table 7, the pll will be declared in lock and the lock detect output will go active. the assertion of sdn will also cause an out of lock condition.
4 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j figure 3. input jitter tolerance specification figure 4. jitter transfer specification 1. bellcore specifications: gr-253- core, issue 2, december 1995. 2. itu-t recommendations: g.958. 3. not specified in gr-253 or g.958. f0 f1 f2 f3 ft 0.15 1.5 15 sinusodal input jitter amplitude (ui p-p) frequency sonet jitter characteristics performance the S3056 pll complies with the jitter specifications proposed for sonet/sdh equipment defined by the bellcore specifications: gr-253-core, issue 2, de- cember 1995 and itu-t recommendations: g.958 document, when used as specified. input jitter tolerance input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 db opti- cal/electrical power penalty. sonet input jitter tolerance requirements are shown in figure 3. jitter transfer the jitter transfer function is defined as the ratio of jitter on the output oc-n/sts-n signal to the jitter applied on the input oc-n/sts-n signal versus fre- quency. jitter transfer requirements are shown in fig- ure 4. the measurement condition is that input sinusoidal jitter up to the mask level in figure 4 be applied. jitter generation the jitter of the serial clock and serial data outputs shall not exceed the value specified in table 7. when a serial data input with no jitter is presented to the serial data inputs. (see table 7.) s t s / c o l e v e l 0 f ) z h ( 1 f ) z h ( 2 f ) z h ( 3 f ) z h k ( t f ) z h k ( 8 40 10 0 60 0 0 60 0 10 0 0 1 4 2 3 2 10 10 30 0 35 20 5 2 30 10 30 0 35 . 65 6 s t s / c o l e v e l 2 , 1 c f ) z h k ( p ) b d ( 8 40 0 0 21 . 0 4 2 3 2 10 0 51 . 0 30 3 11 . 0 fc p jitter transfer frequency acceptable range slope = -20 db/decade
5 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j fibre channel jitter characteristics performance the S3056 pll complies with the jitter specifications proposed for fibre channel equipment defined by the fibre channel methodology for jitter specification. input jitter tolerance input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 db opti- cal/electrical power penalty. fibre channel input jitter tolerance requirements are shown in table 3. system storage disk drive serdes serdes backplane pbc repeaeters cables connectors componet receiver node = a r system host adaptor a t = component transmitter node figure 5. fibre channel system node definition s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u t j d f o t z h k 7 3 6 ( e c n a r e l o t r e t t i j t n e d n e p e d y c n e u q e r f 3 ) z h m 50 1 . 0C p - p i u t j d ) z h m 1 3 5 C z h k 7 3 6 ( e c n a r e l o t r e t t i j c i t s i n i m r e t e d 8 3 . 0C p - p i u t j r ) z h m 1 3 5 C z h k 7 3 6 ( r e t t i j m o d n a r 2 2 . 0C p - p i u t j t r e t t i j l a t o t 0 7 . 0C p - p i u table 3. input jitter tolerance specification at node a r s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u j dr e t t i j c i t s i n i m r e t e d 8 0 . 0p - p i u j tr e t t i j l a t o t 3 2 . 0p - p i u table 4. total jitter generation specification at node a t jitter generation the jitter of the serial clock and serial data outputs shall not exceed the value specified in table 4 when a serial data input with no jitter is presented to the serial data inputs.
6 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p i t a d r e s n i t a d r e s . f f i d l m c i 3 2 . s t u p n i e s e h t n o s n o i t i s n a r t e h t m o r f d e r e v o c e r s i k c o l c . n i a t a d l a i r e s ) . 0 1 e r u g i f e e s ( . d e t a n i m r e t d n a d e s a i b y l l a n r e t n i s s a p y bl t t v li6 4 t u p n i a t a d f o n o i s s i m s n a r t s w o l l a t i . l l p e h t s s a p y b o t d e s u . h g i h e v i t c a . e v i t c a n i s i n d s n e h w y l n o e v i t c a e b l l i w s s a p y b . y r e v o c e r k c o l c t u o h t i w n d s e l g n i s d e d n e l c e p v l i5 4 n e v i r d e b o t t u p n i l c e p k 0 1 d e d n e - e l g n i s a . w o l e v i t c a . t c e t e d l a n g i s d e v i e c e r f o s s o l a e t a c i d n i o t e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n i a t a d l a i r e s e h t n o a t a d e h t , e v i t c a n i s i n d s n e h w . r e w o p l a c i t p o e h t d n a , o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i e b l l i w s n i p ) n / p i t a d r e s ( , e v i t c a s i n d s n e h w . s t u p n i k l c f e r e h t o t k c o l o t d e c r o f e b l l i w l l p . y l l a m r o n d e s s e c o r p e b l l i w s n i p n / p i t a d r e s e h t n o a t a d p k l c f e r n k l c f e r y l l a n r e t n i d e s a i b . f f i d l c e p v l i 6 7 r o l e n n a h c e r b i f t n e l a v i u q e r o ( z h m 4 4 . 9 1 / 2 5 . 5 5 1 . k c o l c e c n e r e f e r g n i t a r e p o l a i t i n i e h t h s i l b a t s e o t d e s u t u p n i ) y c n e u q e r f t e n r e h t e t i b a g i g k c o l c y b d n a t s a s a d e s u o s l a d n a l l p y r e v o c e r k c o l c e h t f o y c n e u q e r f y l l a n r e t n i . e v i t c a n i s i n d s n e h w r o t e s e r g n i r u d , a t a d f o e c n e s b a e h t n i . d e s a i b 1 p a c 2 p a c i 0 4 9 3 e r a s r o t s i s e r d n a r o t i c a p a c r e t l i f p o o l l a n r e t x e e h t . r o t i c a p a c r e t l i f p o o l ) . 4 1 e r u g i f e e s ( . s n i p e s e h t o t d e t c e n n o c n f e r k c ll t t v li7 1 l l i w t u p t u o k c o l c l a i r e s e h t , e v i t c a n e h w . w o l e v i t c a . e c n e r e f e r o t k c o l . ] k l c f e r [ t u p n i k c o l c e c n e r e f e r l a c o l e h t o t k c o l o t d e c r o f e b 0 l e s e t a r 1 l e s e t a r l t t v li 0 2 9 1 ) . 1 e l b a t e e s ( e d o m g n i t a r e p o e h t s t c e l e s . t c e l e s e t a r k l c t s e tl t t v li5 1 o t t c e n n o c . t s e t n o i t c u d o r p r o f d e s u l a n g i s t u p n i t s e t . k c o l c t s e t . h g i h d e l l u p y l l a n r e t n i s i t u p n i s i h t . n o i t a r e p o l a m r o n r o f d n u o r g l e s f e rl t t v li8 1) . 2 e l b a t e e s ( y c n e u q e r f e c n e r e f e r e h t s t c e l e s t s rl t t v li6 1 n - y b - e d i v i d o c v d n a t i u c r i c t c e t e d k c o l s t e s e r . h g i h e v i t c a . t u p n i t e s e r . t s e t n o i t c u d o r p r o f t i u c r i c n e t s e tl t t v li7 4 . t s e t n o i t c u d o r p r o f o c v e h t s e s s a p y b . h g i h e v i t c a . e l b a n e t s e t d e l l u p y l l a n r e t n i s i t u p n i s i h t . n o i t a r e p o l a m r o n r o f d n u o r g o t t c e n n o c . h g i h p o t a d r e s n o t a d r e s . f f i d l m c o 8 2 7 2 a t a d g n i m o c n i e h t f o n o i s r e v d e y a l e d e h t s i l a n g i s s i h t . t u o a t a d l a i r e s t u o k c o l c l a i r e s f o e g d e g n i l l a f e h t n o d e t a d p u ) n / p i t a d r e s ( m a e r t s . ) n / p o k l c r e s ( p o k l c r e s n o k l c r e s . f f i d l m c o 4 3 3 3 t u o a t a d l a i r e s h t i w d e n g i l a e s a h p s i l a n g i s s i h t . t u o k c o l c l a i r e s ) . 8 e r u g i f e e s ( . ) o t a d r e s ( t e d k c o ll t t v lo0 1 k c o l c l a n r e t n i e h t n e h w h g i h t e s . r o t a c i d n i y r e v o c e r k c o l c . t c e t e d k c o l n a s i t e d k c o l . m a e r t s a t a d g n i m o c n i e h t o t n o d e k c o l s a h y r e v o c e r . t u p t u o s u o n o r h c n y s a t u o t s e to3 2. n o i t a r e p o l a m r o n r o f n e p o e v a e l . t u p t u o t s e t table 5. pin assignment and descriptions
7 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d c c v av 3 . 3 +i 7 3 2 4 . y l p p u s r e w o p g o l a n a d n g ad n gi 3 4 , 1 4 , 8 3. n o i t c e n n o c d n g g o l a n a c c vv 3 . 3 +i , 9 , 5 , 1 , 4 2 , 1 2 , 9 2 , 6 2 8 4 , 5 3 , 2 3 . y l p p u s r e w o p d n gd n gi , 1 1 , 8 , 4 , 3 1 , 2 1 , 2 2 , 4 1 , 0 3 , 5 2 4 4 , 6 3 , 1 3 . n o i t c e n n o c d n u o r g table 5. pin assignment and descriptions (continued)
8 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j figure 6. S3056 48 pin tqfp/tep pinout 1 2 3 4 5 7 9 11 36 35 34 33 31 29 27 25 32 30 28 26 14 13 15 16 17 18 19 20 21 22 24 23 47 48 46 45 44 43 42 41 40 39 37 38 12 8 10 6 serdatin serdatip gnd vcc vcc gnd gnd lockdet testen vcc bypass sdn gnd agnd avcc agnd cap1 cap2 avcc agnd gnd gnd testclk rst lckrefn refsel ratesel1 ratesel0 vcc gnd vcc testout gnd vcc serclkop serclkon gnd vcc serdaton gnd vcc gnd serdatop vcc vcc refclkn gnd refclkp S3056 48 pin tqfp/tep top view
9 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j figure 7. 48 pin tqfp/tep package e c i v e dr e w o p x a m e g a k c a p q a j 6 5 0 3 sw m 2 3 8w / c ? 0 5 table 6. thermal management top view
10 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j table 7. performance specifications r e t e m a r a pn i mp y tx a ms t i n un o i t i d n o c y c n e u q e r f g n i t a r e p o o c v 5 2 1 . 28 8 4 . 25 . 2z h g d e k c o l o c v h t i w r e t t i j t u p t u o a t a d k l c f e r o t 8 4 - c o . k l c . f e r z h m 4 4 . 9 1 . k l c . f e r z h m 2 5 . 5 5 1 4 2 - c o . k l c . f e r z h m 4 4 . 9 1 . k l c . f e r z h m 2 5 . 5 5 1 2 1 - c o . k l c . f e r z h m 4 4 . 9 1 . k l c . f e r z h m 2 5 . 5 5 1 3 - c o . k l c . f e r z h m 4 4 . 9 1 . k l c . f e r z h m 2 5 . 5 5 1 8 0 . 0 1 0 . 0 4 0 . 0 5 0 0 . 0 2 0 . 0 5 2 0 0 . 0 5 0 0 . 0 1 0 0 . 0 ) s m r ( i u ) s m r ( i u ) s m r ( i u ) s m r ( i u ) s m r ( i u ) s m r ( i u ) s m r ( i u ) s m r ( i u r e t t i j s m r r e t t i j s m r ) d e t s e t t o n ( r e t t i j s m r ) d e t s e t t o n ( r e t t i j s m r r e t t i j s m r r e t t i j s m r r e t t i j s m r r e t t i j s m r d e k c o l o c v h t i w r e t t i j t u p t u o a t a d 8 4 - s t s n / p i t a d r e s o t 1 0 . 0) s m r ( i u. s t u p n i a t a d l a i r e s n o r e t t i j o n h t i w y c n e u q e r f k c o l c e c n e r e f e r e c n a r e l o t 0 0 1 -0 0 1 +m p p ) 8 4 - c o ( e m i t k c o l n o i t i s i u q c a k l c f e r z h m 4 4 . 9 1 ) e t a r l e n n a h c e r b i f t n e l a v i u q e r o ( k l c f e r z h m 2 5 . 5 5 1 ) e t a r l e n n a h c e r b i f t n e l a v i u q e r o ( 0 0 8 1 0 5 2 c e s . % 0 2 f o y t i s n e d n o i t i s n a r t m u m i n i m . d e t s e t t o n t u b d e e t n a r a u g p u d e r e w o p y d a e r l a e c i v e d h t i w . k l c . f e r d i l a v d n a k c o l c e c n e r e f e r e l c y c y t u d t u p n i 0 40 6i u f o % s e m i t l l a f & e s i r k c o l c e c n e r e f e r 5 . 1s n. e d u t i l p m a f o % 0 8 o t % 0 2 s e m i t l l a f & e s i r t u p t u o l m c 0 0 10 5 1s p0 5 , % 0 8 o t % 0 2 w . p a c f p 1 , d a o l e h t h c i h w t a e c n e r e f f i d y c n e u q e r f k l c f e r ( k c o l f o t u o s e o g l l p o c v n w o d d e d i v i d e h t o t d e r a p m o c ) k c o l c 0 5 40 0 60 7 7m p p e h t h c i h w t a e c n e r e f f i d y c n e u q e r f k l c f e r ( k c o l o t n i s e o g l l p e v i e c e r o c v n w o d d e d i v i d e h t o t d e r a p m o c ) k c o l c 0 2 20 0 30 9 3m p p
11 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j r e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c e c n a r e l o t r e t t i j 8 4 - s t s 4 . 05 . 0i u z h m 5 < f < z h m 1 2 = n r e t t a p a t a d 7 s b r p 1 - e c n a r e l o t r e t t i j 4 2 - s t s e c n a r e l o t r e t t i j 2 1 - s t s 4 . 06 . 0i u z h m 5 < f < z h k 0 5 2 2 = n r e t t a p a t a d 7 s b r p 1 - e c n a r e l o t r e t t i j 3 - s t s 4 . 08 . 0i u z h m 1 < f < z h k 5 6 2 = n r e t t a p a t a d 7 s b r p 1 - table 8. jitter tolerance specifications note: output propagation delay time of high speed cml outputs is the time in pico seconds from the cross-over point of the reference signal to the cross-over point of the output. serdatop/n serclkop t su t h 50% figure 8. receiver output timing diagram r e t e m a r a pn i mp y tx a ms t i n un o i t i d n o c t u s ) s p b m 5 2 1 2 ( l e n n a h c e r b i f / 8 4 - c o ) s p b m 5 . 2 6 0 1 ( l e n n a h c e r b i f / 4 2 - c o 2 1 - c o 3 - c o 0 0 1 0 5 2 0 0 5 0 0 5 2 s p. 8 e r u g i f e e s t h ) s p b m 5 2 1 2 ( l e n n a h c e r b i f / 8 4 - c o ) s p b m 5 . 2 6 0 1 ( l e n n a h c e r b i f / 4 2 - c o 2 1 - c o 3 - c o 0 0 1 0 5 2 0 0 5 0 0 5 2 s p. 8 e r u g i f e e s table 7. performance specifications (continued)
12 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j table 10. recommended operating conditions table 11. absolute maximum ratings r e t e m a r a pn i mp y tx a ms t i n u ) l a i r t s u d n i ( s a i b r e d n u e r u t a r e p m e t t n e i b m a0 4 -5 8 +c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 3 1 . 33 . 35 6 4 . 3v n i p t u p n i l t t v l y n a n o e g a t l o v0v c c v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v i c c t n e r r u c y l p p u s 1 7 8 10 4 2a m r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1 +c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 . 0 -5 6 4 . 3v n i p t u p n i l t t v l y n a n o e g a t l o v5 . 0 -v c c v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v t n e r r u c k n i s t u p t u o l t t v l8a m t n e r r u c e c r u o s t u p t u o l t t v l8a m 1. outputs open. electrostatic discharge (esd) ratings the S3056 is rated to the following voltages based on the human body model: 1. all pins are rated 100 volts except pin # 40 (cap1) and pin # 39 (cap2). adherence to standards for esd protection should be taken during the handling of the devices to ensure that the devices are not damaged. the standards to be used are defined in ansi standard ansi/esd s20.20-1999, "protection of electrical and electronic parts, assemblies and equipment." contact your local fae or sales representative for applicable esd application notes. r e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c t j e c n a r e l o t r e t t i j t u p n i l a t o t9 9 5s p. z 3 . 2 0 8 e e e i n i d e i f i c e p s s a t j d r e t t i j t u p n i c i t s i n i m r e t e d e c n a r e l o t 0 7 3s p. z 3 . 2 0 8 e e e i n i d e i f i c e p s s a table 9. gigabit ethernet jitter specifications
13 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j table 14. lvttl input/output dc characteristics l o b m y sn o i t p i r c s e dn i mp y tx a mt i n us n o i t i d n o c v h i e g a t l o v h g i h t u p n i0 . 25 6 4 . 3v v l t t c c x a m = v l i e g a t l o v w o l t u p n i0 . 08 . 0v v l t t c c x a m = i h i t n e r r u c h g i h t u p n i0 5a v n i v 4 . 2 = i l i t n e r r u c w o l t u p n i0 0 5 -a v n i v 5 . 0 = v h o e g a t l o v h g i h t u p t u o4 . 2v v h i n i m = v l i x a m = i h o a 0 0 1 - = v l o e g a t l o v w o l t u p t u o5 . 0v v h i n i m = v l i x a m = i ol a m 0 . 1 = note: all parameters are specified with respect to the source termination and ground with v ttl = max. = 3.465 v. table 13. cml output dc characteristics table 12. cml input dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c d v f f i d n i g n i w s e g a t l o v t u p n i l a i t n e r e f f i d0 0 30 0 9 1v m. 9 e r u g i f e e s d v e l g n i s n i g n i w s e g a t l o v t u p n i d e d n e - e l g n i s0 5 10 5 9v m. 9 e r u g i f e e s r f f i d e c n a t s i s e r t u p n i l a i t n e r e f f i d0 80 0 10 2 1 w r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l o ) a t a d ( e g a t l o v w o l t u p t u o l m c v c c 0 . 1 - v c c 5 6 . 0 - v0 0 1 w . e n i l - o t - e n i l v h o ) a t a d ( e g a t l o v h g i h t u p t u o l m c v c c 5 3 . 0 - v c c 2 . 0 - v0 0 1 w . e n i l - o t - e n i l d v f f i d t u o ) a t a d ( e g a t l o v l a i t n e r e f f i d t u p t u o l a i r e s l m c g n i w s 0 0 80 0 6 1v m 0 0 1 w . e n i l - o t - e n i l . 9 e r u g i f e e s d v e l g n i s t u o ) a t a d ( d e d n e - e l g n i s t u p t u o l a i r e s l m c g n i w s e g a t l o v 0 0 40 0 8v m 0 0 1 w t a e n i l - o t - e n i l . 9 e r u g i f e e s . s p b g 5 . 2 v l o ) k c o l c ( e g a t l o v w o l t u p t u o l m c v c c 5 . 1 - v c c 5 8 . 0 - v0 0 1 w . e n i l - o t - e n i l v h o ) k c o l c ( e g a t l o v h g i h t u p t u o l m c v c c 5 . 0 - v c c 5 2 . 0 - v0 0 1 w . e n i l - o t - e n i l d v f f i d t u o ) k c o l c ( e g a t l o v l a i t n e r e f f i d t u p t u o l a i r e s l m c g n i w s 0 0 80 0 8 1v m 0 0 1 w . e n i l - o t - e n i l . 9 e r u g i f e e s d v e l g n i s t u o ) k c o l c ( d e d n e - e l g n i s t u p t u o l a i r e s l m c g n i w s e g a t l o v 0 0 40 0 9v m 0 0 1 w t a e n i l - o t - e n i l . 9 e r u g i f e e s . z h g 5 . 2
14 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i e g a t l o v w o l t u p n i v c c 0 0 . 2 C v c c 4 . 1 C v v h i e g a t l o v h g i h t u p n i v c c 2 . 1 C v c c 5 . 0 C v i l i t n e r r u c w o l t u p n i0 0 1 C0a i h i t n e r r u c h g i h t u p n i0 5 +0 5 3a table 15. single ended lvpecl input dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i e g a t l o v w o l t u p n i v c c 0 0 . 2 C v c c 4 . 1 C v v h i e g a t l o v h g i h t u p n i v c c 2 . 1 C v c c 5 . 0 C v i l i t n e r r u c w o l t u p n i0 0 3 C0a v l i v = c c 2 C i h i t n e r r u c h g i h t u p n i0 5 C0 0 1a v h i v = c c 5 . 0 C d v f f i d n i g n i w s e g a t l o v t u p n i l a i t n e r e f f i d0 0 30 0 2 1v m. 9 e r u g i f e e s d v e l g n i s n i g n i w s e g a t l o v t u p n i d e d n e - e l g n i s0 5 10 0 6v m. 9 e r u g i f e e s table 16. internally biased differential lvpecl input ac characteristics figure 9. differential voltage measurement note: v(+) C v(-) is the algebraic difference of the input signals. v(+) v(? v(+) ?v(-) 0.0v v swing v d = 2 x v swing
15 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j figure 12. +5v differential pecl driver to S3056 reference clock input ac coupled termination vcc -0.5 v vcc -0.5 v S3056 refclkp/n +5 v 100 330 330 0.01 f 0.01 f +3.3 v 155 mhz oscillator zo=50 zo=50 vcc -0.5 v vcc -0.5 v S3056 serdatip/n +5 v 100 330 330 0.01 f 0.01 f +3.3 v zo=50 zo=50 figure 10. +5v differential pecl driver to S3056 differential cml input ac coupled termination +3.3 v S3056 serdatop/n serclkop/n +3.3 v s3057/s3067 serdatip/n serclkip/n vcc -0.5 100 vcc -0.5 zo=50 zo=50 figure 11. S3056 differential cml output to s3057/s3067 terminations
16 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j figure 13. +3v differential lvpecl driver to S3056 reference clock input dc coupled termination vcc -0.5 v vcc -0.5 v S3056 refclkp/n +3 v 100 150 150 +3.3 v 155 mhz oscillator/ 155mck from s3057 zo=50 zo=50 cap1 56 10 f cap2 56 S3056 figure 14. loop filter capacitor connections
17 S3056 multi-rate sonet/sdh clock recovery unit october 31, 2000 / revision j ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s6 5 0 3p e t / p f q t n i p 8 4 C t t x xxxx xx prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 2000 applied micro circuits corporation d151/r293 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800)755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1

▲Up To Search▲

Price & Availability of S3056

	To Download S3056 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .